Import Environment Variables: Invoke the following alias to establish system variables pointing to Synopsys executables. If you do not have this file you can copy it from my public directory by entering cp ~ciletti/public/synopsys_info/.synopsys_pt.setup ~/synopsys_designs This will copy the PrimeTime setup file to your synopsys_designs directory, provided that it is located in your home directory and that you execute the copy command from that context.Ĭ. To list hidden files enter Is -al at the command line. synopsys_pt.setup Note: This is a hidden file. Create support files: When you are setting up your environment for Synopsys you will need to be sure that you have the following support file in your synopsys_designs directory. In the Unix environment, change to your synopsys_designs directory. The naming convention within our cell library is consistent in the use of names and port numbers with names.a. Fortunately, small designs may use only a few library cells. For example, the nanf201 2-input inverter has the following formal port names (O, A1, B1), where O is the output. If you are working with a gate-level source file that has not been exported from Design Analyzer, you must pull the formal port names from the module declarations within the cell library source file, and used them in creating your name associations. B(b)) where S, C, a, b are the formal names that were used in the declaration of Add_half, and sum, c_out, a, b are the actual variables in the context of the parent module in which Add)half is instantiated. You will not get a warning message! 1įor example, here's how name association works in an instantiation of a module named Add_half: Add_half M1 (.S(sum). Failing to observe this (apparently undocumented feature) will lead to 0 delay paths when you execute report_timing (such modules are treated as "black boxes" with no timing arcs), as the system appears to ignore the library cell delays if the modules use position association instead of name association. It appears to be necessary that your Verilog description be either a gate-level database file (.db) or a Verilog file generated by Design Analyzer (the Synopsys synthesis tool), or a Verilog source file in which you have used name association at the ports of the modules in the design (i.e.formal_name(actual_name)).
This discussion assumes that you have an account on the workstations in the VLSI Circuit Design Lab and that you have created a directory called synopsys_designs, where you exercise Design Compiler to synthesis Verilog descriptions to produce a netlist(.v) and/or a database file (.db).
This tutorial will use but not provide an in-depth coverage of the Tool command Language (TCL). electrical loading rules), specify environmental attributes, and perform timing analysis.
#SYNOPSYS PRIMETIME TUTORIAL HOW TO#
As a user, you will need to know how to read a design, link a design to libraries, establish constraints on the design (e.g. PrimeTime performs full-chip static timing analysis with high speed and low memory utilization compared to Design Compiler. See class notes for a background discussion of timing analysis. These user notes provide a brief introduction to the use of PrimeTime, the Synopsys static timing analysis (STA) tool. Ciletti Department of Electrical and Computer Engineering University of Colorado at Colorado Springs Rev 11-27-2000 Tutorial Notes Synopsys PrimeTime Static Timing AnalyzerM.D.
Department of Electrical and Computer Engineering University of Colorado at Colorado Springs "Engineering for the Future"